Title, Reti logiche. Authors, M. Morris Mano, Charles R. Kime. Publisher, Pearson Edication Italia, ISBN, , Length, Page 1. RETI LOGICHE. Sito del corso: · Page 2. 2. Design of Integrated Digital Systems. System Level. Register Transfer Level. Suppose that input variable changes are spaced such that the effects of a change in one variable is permitted to propagate throughout the circuit before another.
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Morris Mano, Kime Charles – Reti Logiche
Text size Normal Large. Analysis and synthesis of sequential circuits. Introduction to the use of the microcontroller. Laboratory exercises on microcontroller-based digital electronics. In addition to Units 1 and 2, Unit 3: Lecture Notes by Andrea Scorzoni see Unistudium, with password. Kime, Reti Logiche 4a ed.
Kime, Reti Logiche 2a ed. Unit 1 e 3: Stroustrup, Linguaggio, libreria standard, principi di programmazione, Pearson Italia. Ritchie, Il linguaggio C 2a ed. Brambilla, Introduzione ai circuiti integrati digitali, Zanichelli-Telettra. Schilling, Elettronica integrata digitale, Gruppo Editoriale Jackson.
Nicolic, Circuiti integrati digitali – L’ottica del progettista, 2a ed. Zappa, Elettronica Digitale, Esculapio, Educational objectives 9 CFU class. Prerequisites To undergo the final exam of the class you do not need formal pre-requirements. Students attending the laboratory should have taken the rrti on safety in working places.
Teaching methods The lectures are organized as kkime During each lecture the students are distributed over 10 lab benches equipped with personal computers and laboratory instrumentation. The students will attend about 8 guided lab classes, 3 hours each.
Most of the lab classes will be concluded with a team-classwork: At the end of the guided lab lectures the students willing to perform further individual laboratory work will be asked to arrange an appointment with the educator.
Logifhe verification modality 9 CFU class. The exam consists of a written assignment, max. The final score can only be registered provided the lab exam is passed. The total mark of the 12 CFU exam is calculated as the weighted average of the marks of the written assignment and that of the oral exam. The weigths are calculated as follows: Therefore the final score is calculated as follows: Models for the study of digital systems.
Octal and hexadecimal systems. Conversion among numerical systems. Binary and alphanumerical codes. Exercises on the numerical systems and code conversion. Classification of logic circuits. Functionally complete sets of logic operators.
Two-level simplification through Karnaugh maps, cost minimization through algebraic manipulation of expressions multi-level circuits. Exclusive OR and parity.
Classic design methodology of combinational circuits. Limits of the classic design methodology for combinational circuits: One’s and Two’s complement representation.
Binary adder and subtractor. Hints at a hardware description language VHDL. Exercises on combinational logic circuits. Mealy and Moore classification. Hints on asynchronous logic circuits and static hazards. Design methodology for synchronous logic circuits.
Logicye diagram and table, state coding and transition table, map of state and output variables, next state and output expressions, logic diagram. Synchronous circuits with synchronous and asynchronous inputs. Elementary retl for sequential elaboration: The SPI serial interface. Exercises on synchronous sequential circuits. ROMs and their architecture. Examples of programmable logic circuits: Synthesis of combinational logic circuits with PLA.
Addressing methodologies for memories, address decoding. Feti on memory address decoding. Introduction to the use of electronic devices and of the microcontroller 2 lab CFU, about 24 hours.
Getting acquainted with laboratory instrumentation: Serial communication through UART and interaction with a personal computer; 7. Digital electronics loyiche CFU, about 21 hours – Circuits for the elaboration of digital signals: Static and dynamic power consumption. Approximate equations for the channel current. Analysis of main non-idealities: Static CMOS gates, pass-transistor and related gates, transmission gate. Interfacing between different digital families.
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Università degli Studi di Perugia
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The lectures are organized as follows: